processor (Total 131178 Patents Found)

A signal processor for use in a small, lightweight radar-guided missile to provide a discrete Fast Fourier Transform (FFT) on received radar return signals. The radar return signal are converted into a sequence of binary digits enabling a simple decoder to perform complex addition and subtraction processing, thereby mi...
A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two types of control procedures selected from HDLC procedure, BI-SYNC procedure and start-stop synchronous procedur...
In order to gather, store temporarily and efficiently deliver (if needed) safestore information in a fault tolerant central processing unit having data manipulation circuitry including a plurality of software visible registers, a shadow set of the software visible registers are used in conjunction with shadowing and pa...
Input/output (I/O) apparatus for a system is disclosed utilizing a digital processor for entering analog, digital and discrete data into the processor and receiving analog, digital and discrete data from the processor via an I/O data bus. A plurality of analog data signals are applied sequentially to an analog to digit...
In an asynchronous access system for a multiprocessor system having a plurality of processor modules connected to a system bus and at least one shared memory module connected to the system bus, each of the processor modules includes a processor and an internal buffer. The processor writes data into the internal buffer,...
A processing unit for executing parallel cumulative absolute difference operations in a first mode, and an inner product operation in a second mode, includes an input bus group for receiving first input data, second input data, and third input data. A plurality of processor elements are coupled to the input bus group, ...
A digital signal processor for determining a property of a material flowing through a conduit. The digital signal processor of this invention receives signals from two pick-off sensor mounted at two different points along a flow tube at a first sample rate. The signals are converted to digital signals. The digital sign...
A signal processor eliminates sidelobe response from signals produced by a spaced antenna array that forms a single beam using spatial frequencies. The signal processor also produces error signals. The signal processor uses a phase coherent local oscillator to simultaneously convert the wavefront signal from each eleme...
A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has sever...
Grid members for supporting a bale of hay within the tub of a tilt-tub bale processor are fixed to the floor of the tiltable tub and extend across an opening in the floor in order to control the feed rate of crop materials toward the chopping and disintegrating rotor. The tub is shiftable to any one of a number of slig...
An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage...
Each of processors in a multiprocessor system has a circuit for sending a synchronizing signal to a storage controller (SC) connected thereto when executing a synchronization instruction such as a start, end or barrier synchronization instruction. Each of the SCs has a circuit for notifying the corresponding processor ...
A program-controlling processing unit executes instructions stored in memory. A special instruction type is provided for selectively retrieving an element from memory in dependence on the value of input data subject of the instruction. Each instruction of this type has a header identifying the instruction type, and a b...
A method for integrating Asynchronous Transfer Mode (ATM) and frame-based traffic flows within a telecommunications network is disclosed. The telecommunications network includes a network processor having upside processing means for delivering an incoming flow from the telecommunications network to a switch and downsid...
An universal multimedia book interfacing device is disclosed in this invention. This device is used for operation with a multimedia book. The interfacing device includes a first adapting connector provided with connection compatibility for electrically connecting to several different multimedia books. Each multimedia b...
A camera has an image sensor for capturing an image in a Bayer image space and a processor for converting the captured image to an output space. Coordinates of the input space are mapped to the coordinates of the output space by dividing the output space coordinates by the number of pixels in the output space per input...
A system and method are disclosed for an optical backplane in an electronic processor that comprises of a plurality of processing units. The backplane is comprising of a network of optical waveguides which can guide polarized light. Furthermore, the backplane has magneto optic routers for steering light at the vertexes...
A folded back portion flattening device includes a gripper and a presser. The gripper grips a sheet bundle formed into a booklet with the folded back portion protruding from the gripper. The presser presses the folded back portion of the sheet bundle gripped by the gripper, and includes pressing rollers which have pres...
An hardware emulation environment is disclosed wherein software execution is accelerated by switching memory and/or peripheral and clock implementation from the hardware emulator toga faster running processor board coupled to the hardware emulator. A switch is positioned between the hardware emulator and a processor ru...
A device for protecting data for operating or controlling functions of an operating system, process, equipment, and/or a machine, which is stored in a switching arrangement that consists of electronic components and a processor, wherein the switching arrangement is mounted on a printed circuit board inside a housing or...
Systems and methods that measure the delay (latency) through a digital processor or circuit. A waveform generator outputs a primary (chirp) signal to the digital circuit, along with an auxiliary pulse signal to a delay circuit. The auxiliary signal corresponds to a sample of the primary signal that is input to and outp...
An endoscope processor comprising an image signal receiver, a calculator, an amplifier, and a noise reduction unit, is provided. The image signal receiver receives a raw image signal. The image signal is generated by an imaging device when the imaging device captures an optical image of an object. The calculator calcul...
An electronic communication and/or multimedia device comprises a central processing unit controlling the operation of said device, wherein in a standard mode the operation of the device is carried out on the basis of data stored in the first memory said device. In a reduced mode of said device, a part of the data store...
A technique for performing cache injection includes monitoring, at a cache, addresses on a bus. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache. A replacement ...
A processor includes a plurality of first processing units. A direct memory access unit is coupled to at least one first processing unit of the plurality of first processing units. The processor includes a plurality of data storage units. A second processing unit is adapted to process data from at least one data storag...
A mobile communication method according to the present invention includes the steps of: (A) activating a first timer, when the radio base station (eNB) transmits a downlink data signal to the mobile station (UE) operating in a continuous reception cycle; and (B) changing a reception cycle of the mobile station (UE) fro...
Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerate SBR and other audio processing. In addition to the instruction extensi...